In recent years, the home PC has the highest growth rate in the PC market. The home PC provides not only the personal productivity enhancement but also communication, entertainment and education. The technology of the home PC becomes more complicated than the traditional business PC, which provides only the office productivity. Facing the introduction of 32-bit Windows 95 operating system, the design of home PC is no longer a trivial job to most computer designers. Take an example of the following challenge: home PC needs not only a very low cost structure to be mass manufactured but also a very high performance to run various applications. The key components of PC are consisted of four parts, namely CPU, memory, system core logic and peripheral subsystem. CPU is currently dominated by Intel Corp., and most of the computer system designers do not have much freedom to exploit in this area. The industry standard PCI bus has improved the I/O devices to a new high performance level. It will not change to a new bus within a foreseeable near future. The only part left to the computer designer is the memory subsystem. These include both the memory controller inside the system logic and DRAM itself.
Conventional wisdom on the memory subsystem is that the system core logic needs to support a very advanced cache memory architecture to fully exploit the CPU performance. The approach usually becomes prohibited in the home PC because of the high cost of cache Static Random Access Memory (SRAM). If one is requested to implement a low cost home PC, the cache memory feature will be omitted in the first place. But the cacheless system may cost the performance degradation from 20% up to 50%. The new DRAM technology like Extended Data Out(EDO) DRAM can only improve performance by less than 5%. Even Burst-EDO(BEDO), Synchronous DRAM or RAMBUS DRAM can only improve performance by less than 10%. Further details of the BEDO DRAM may be referred in MICRON CO.'s data sheet regarding to MT4LC2M8F4 product. Further details of the Synchronous DRAM may be referred in NEC CO.'s data sheet regarding to PD4516421, PD4516821 or PD4516161 product. None of current DRAM technologies can really solve the problem of performance degradation when cache memory is not implemented within the system. The reason for the minor improvement with those new DRAM technologies is due to the fact of bad memory locality in the behavior of 32-bit operating system. The bad memory locality causes a huge overhead both to the cache-miss rate and DRAM page-miss rate. In system with BEDO DRAM, synchronous DRAM or RAMBUS DRAM, condition of page-miss interrupts burst-type transfer frequently. One alternative is to use a multi-bank DRAM architecture with page interleave scheme to improve the page-hit rate. Such scheme may be totally understood by referring U.S. Pat. No. 4,924,375. But this approach will yield a bigger die size due to inefficient overhead of its peripheral circuits. As a result, the cost of current new type DRAMs, which are implemented intentionally to replace the cache SRAM in the computer system, may easily exceeds the cost of cache SRAM. Therefore, low cost and, at the same time, high performance is simply not available from the conventional wisdom up to date.
In order to yield a high performance comparable to a typical cache SRAM system, two basic goals: 1) no memory page-miss overhead and 2) high data burst rate, must be met. Based on the above recitations, the inventor of the instant invention invents a new DRAM architecture which delivers both a low cost implementation and a high performance comparable to the cache SRAM. With this invention, two basic requirements are still met: 1) backward-compatible to the current fast page mode DRAM single in-line memory module (SIMM) and 2) similar single bank architecture of the current fast page mode DRAM in order to leverage the current lowest cost infrastructure from the fast page mode DRAM. In this new DRAM of the invention, no cache TAG SRAM is used, since both TAG comparison and its associated costs are extra overhead to the memory subsystem. Further details of the fast page mode DRAM may be referred in U.S. Pat. No. 5,265,236 or MICRON CO.'s data sheet regarding to MT4LC4M4A1/B1(S) product.
As recited hereinafter, a hidden precharge pseudo cache (HPPC) DRAM is disclosed to meet all above design requirements or goals. This new technology of HPPC DRAM brings a new level of high performance to all low cost PCs. The pin definitions of HPPC DRAM is comparable to the state-of-art fast page mode DRAM to allow constructing a backward-compatible DRAM SIMM. Further details of the pin layout of the fast page mode DRAM may be referred in MICRON CO.'s data sheet regarding to MT4LC4M4A1/B1(S) product. Further details of the fast page mode DRAM SIMM module may be referred in MICRON CO.'s data sheet regarding to MT8LD132(S) or MT16LD232(S) product.